一种用于背板互连的10 Gbit/s接口电路

基于SMIC 40 nm CMOS工艺,提出了一种用于背板互连的10 Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10 Gbit/s,传输信道在Nyquist频率(即5 GHz)处的衰减为22.4 dB。在1.1 V电源电压下,判决器Slicer输入端信号眼图的眼高为198 mV,眼宽为83 ps。FFE的功耗为31 mW,接收机前端放大器的功耗为1.8 mW,DFE的功耗为5.4 mW。

A 10 Gbit/s Interface Circuit for Backplane Interconnection

A 10-Gbit/s I/O interface circuit for backplane interconnection was designed in SMIC 40 nm CMOS process. The interface circuit consisted of a feed-forward equalizer (FFE), a receiver front-end amplifier and a decision feedback equalizer (DFE). The FFE was designed to pre-distort the transmitter signal. The DFE was designed to cancel the large residue inter-symbol interference (ISI). The effects of FFE and DFE on ISI were mainly analyzed. A novel FFE was proposed to reduce the attenuations. Therefore, the signals had large amplitudes at the receiver, which could obtain right decisions to remain a low bit error rate (BER). The measured results showed that the data rate was 10 Gbit/s and the channel had a 22.4 dB attenuation at the 5 GHz Nyquist frequency. With 1.1 V supply voltage, the eye diagram of Slicer input signal had a height of 198 mV and a width of 83 ps. The power consumption was 31 mW for the FFE, 1.8 mW for the receiver front-end amplifier, and 5.4 mW for the DFE.