分相位时钟组的高速数据采样

高速的数模混合电路设计通常要求对模拟信号产生的数据进行实时准确采样。介绍了基于分相位时钟组的高速数据采样电路,并手工设计一款高性能锁相环和延时锁相环来产生数字电路时钟组,加载特定的逻辑综合约束,最终使用动态仿真工具进行电路仿真。仿真结果表明在使用分相位时钟组实现高速数据采样的同时,还可以有效地改善时序和布局布线的压力。

High-speed Data Sampling by Multi-phase Clocks in IC Design

High-speed mix of digital and analog circuits should accurately sample the data which is produced by the analog circuits in real time.High-speed data sampling can be solved by the multi-phase clocks.In the physical design stage,the clock sources can be provided by high-performance phase locked loop and delayed phase locked loop which are designed manually;in the logic synthesis stage,the clock constrains are consistent,and the group clock can be simulated by the dynamic simulation tools in multi-models.The time sequence can be improved and the pressure of layout wiring can be mitigated effectively by the multi-phase clocks.