| Abstract: | By analysing the output characteristics of individual pass transistors in a transmission gate (TG) based CMOS full adder, it is possible to use fewer transistors to implement addition. Various simplified full adders with different numbers of transistors are tested using Pspice simulation. Comparison of these full adders is based on the maximum allowable offset voltages of each node in the full adder configuration. The simplest architecture with a driving output inverter only requires 14 transistors instead of the original 22, as proposed by Zhuang and Wu. Since the simplest architecture is conditional, minimizing the threshold voltage of pass transistors and a design that is more robust are desired in order to increase the fabrication yield. A 16-transistor full adder is optimized for the trade-off between area and reliability. By converting two transistors of an XOR gate into an inverter, this full adder is demonstrated to perform better than an 18-transistor full adder, especially while the inputs are degraded. |
