| 甚短距离光传输系统并行帧同步电路的设计与实现 |
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| 引用本文： | 曾敏,朱恩,王晓明,苗澎,王志功.甚短距离光传输系统并行帧同步电路的设计与实现[J].电子工程师,2004,30(4):26-29. |
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| 作者姓名： | 曾敏 朱恩 王晓明 苗澎 王志功 |
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| 作者单位： | 东南大学射频与光电集成电路研究所,江苏省,南京市,210096 |
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| 基金项目： | 国家高技术研究发展计划(863计划) |
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| 摘 要： | 根据甚短距离(VSR)光纤传输系统中转换接收芯片帧同步系统的设计思想,参考ITU-T关于同步数字系列(SDH)技术的建议,分析了帧同步系统的关键性能参数,结合具体硬件电路的设计,选取了合适的参数.在此基础上,用Verilog HDL语言设计了帧同步系统,选用Altera公司的Stratix EPlS25F780C5,对电路进行了仿真模拟.作为VSR实验系统关键电路之一,帧同步系统通过在系统测试,测试结果显示该帧同步系统能够在实际中应用.
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| 关 键 词： | 甚短距离 光纤传输系统 帧同步系统 同步数字系列 现场可编程门阵列 |
| 修稿时间： | 2004年2月11日 |
Design and Implementation of a Parallel Frame Aligner in VSR System |
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| Zeng Min,Zhu En,Wang Xiaoming,Miao Peng,Wang Zhigong.Design and Implementation of a Parallel Frame Aligner in VSR System[J].Electronic Engineer,2004,30(4):26-29. |
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| Authors: | Zeng Min Zhu En Wang Xiaoming Miao Peng Wang Zhigong |
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| Abstract: | Basing on the design philosophy of the frame aligner in receive module of conversion IC in VSR optical transmission system, and according to the recommendation of ITU T about SDH, several parameters, which are important to the performance of the frame aligner, are analyzed and chosen with consideration of the circuit used. Basing on the analysis, the frame aligner is designed using Verilog HDL, and FPGAs of Stratix EP1S25F780C5 from Altera corporation. As one of the important parts of the VSR experimental system, the simulation and downloading to the device are accomplished. It is demonstrated that the design of the frame aligner is applicable to the VSR system. |
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| Keywords: | very short reach optical transmission system frame aligner SDH FPGA |
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