| 200MSPS数字脉冲压缩模块设计与实现 |
| |
| 引用本文： | 陈铠,周海斌,刘刚.200MSPS数字脉冲压缩模块设计与实现[J].电子工程师,2009,35(2):19-21,48. |
| |
| 作者姓名： | 陈铠 周海斌 刘刚 |
| |
| 作者单位： | 南京电子技术研究所,江苏省南京市,210013 |
| |
| 摘 要： | 介绍了基于Xilinx公司FPGA（现场可编程门阵列）实现高速实时数字脉冲压缩处理的设计方法。本数字脉冲压缩模块由3片FPGA级联，分别完成脉冲压缩运算中的FFT（快速傅里叶变换）、复数乘窗和IFFT（快速傅里叶反变换）功能。在Xilinx器件上实现了数字脉冲压缩算法。通过与MATLAB仿真结果比较，该数字脉冲压缩模块很好地实现了32k点的块浮点数字脉冲压缩功能，吞吐率达到200MSPS（百万次采样每秒）。
|
| 关 键 词： | 数字脉冲压缩 FPGA FFT 块浮点 |
Design and Realization of 200MSPS Digital Pulse Compression Module |
| |
| CHEN Kai,ZHOU Haibin,LIU Gang.Design and Realization of 200MSPS Digital Pulse Compression Module[J].Electronic Engineer,2009,35(2):19-21,48. |
| |
| Authors: | CHEN Kai ZHOU Haibin LIU Gang |
| |
| Affiliation: | Nanjing Research Institute of Electronics Technology;Nanjing 210013;China |
| |
| Abstract: | In this paper,a design method of high-speed,real-time digital pulse compression module based on Xilinx FPGA devices is introduced.This digital pulse compression module consists of three FPGA devices,separately realizing FFT,complex-multiplication and IFFT function.On the basis of analysing and designing each function sub-module,a digital pulse compression algorithm is realized on Xilinx FPGAs.Compared with the MATLAB simulation results,our module can accomplish function of 32k points digital pulse compressi... |
| |
| Keywords: | FPGA FFT |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
