| 基才FPGA的DDSIP核设计 |
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| 引用本文： | 石建平.基才FPGA的DDSIP核设计[J].电子设计工程,2012,20(5):184-186,189. |
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| 作者姓名： | 石建平 |
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| 作者单位： | 毕节职业技术学院,贵州毕节,551700 |
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| 摘 要： | 以Ahera公司的QuartusⅡ7．2作为开发工具，研究了基于FPGA的DDSIP核设计，并给出基于SignalTapⅡ嵌入式逻辑分析仪的仿真测试结果。将设计的DDSIP核封装成为SOPC Builder自定义的组件．结合32位嵌入式CPU软核NiosⅡ，构成可编程片上系统（SOPC），利用极少的硬件资源实现了可重构信号源。该系统基本功能都在FPGA芯片内完成，利用SOPC技术，在一片FPGA芯片上实现了整个信号源的硬件开发平台，达到既简化电路设计、又提高系统稳定性和可靠性的目的。
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| 关 键 词： | 直接数字频率合成 现场可编程门阵列 Nios Ⅱ 可编程片上系统 |
Design of DDS IP core based on FPGA |
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| SHI Jian-ping.Design of DDS IP core based on FPGA[J].Electronic Design Engineering,2012,20(5):184-186,189. |
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| Authors: | SHI Jian-ping |
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| Affiliation: | SHI Jian-ping(Bijie Vocational and Technical College,Bijie 551700,China) |
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| Abstract: | The method of developing DDS IP core based on FPGA is studied in this paper making use of development tools Quartus II 7.2 of Altera company,the simulation result is also given.Taking Nios II soft-core as a CPU and combining a DDS IP core that is encapsulated in SOPC Builder component,a system on programmable chip(SOPC) is built to realize a signal generator.Most of the functions are completed in the FPGA,using SOPC technology to design hardware development platform of signal generator with only one FPGA chip so as to simplify design and to develop the stability and reliability of the system. |
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| Keywords: | Direct Digital Frequency Synthedsis （DDS） Field Programmable Gate Array （FPGA） Nios Ⅱ System on a Programmable Chip （SOPC） |
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