| 异步时序逻辑电路的设计方法探讨 |
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| 引用本文： | 黄建春,张君梅. 异步时序逻辑电路的设计方法探讨[J]. 电气电子教学学报, 2006, 28(3): 39-41 |
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| 作者姓名： | 黄建春 张君梅 |
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| 作者单位： | 湖南文理学院,电气工程系,湖南,常德,415000;湖南文理学院,电气工程系,湖南,常德,415000 |
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| 摘 要： | 在传统的同步时序电路设计方法的基础上，提出了一种新的异步时序电路的设计方法。该方法直接从时序电路的时序波形图，获得触发器的触发脉冲；根据时钟信号作用下引起的状态转换，填写次态卡诺图。其特点是原理简单，易于理解，使设计更加直观清楚。
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| 关 键 词： | 异步时序逻辑电路 时钟信号 次态卡诺图 时序波形图 |
| 文章编号： | 1008-0686（2006）03-0039-03 |
| 收稿时间： | 2006-04-01 |
| 修稿时间： | 2006-05-23 |
A New Method for Designing Asynchronous Sequential Logic Circuit |
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| HUANG Jian-chun,ZHANG Jun-mei. A New Method for Designing Asynchronous Sequential Logic Circuit[J]. Journal of Electrical & Electronic Engineering Education, 2006, 28(3): 39-41 |
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| Authors: | HUANG Jian-chun ZHANG Jun-mei |
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| Affiliation: | Department of Electrical Engineering, Hunan University of Arts and Science, Changde 415000, China |
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| Abstract: | On the base of the traditional approaches for designing synchronous sequential circuits, a new approach for designing asynchronous sequential logic circuit is proposed in this paper where the trigger pulses can be directly obtained from sequential waveforms in sequential circuits, and the next state Karnaugh maps can be acomplished according to the state transformations caused by clock signals. The principle of this approach is easy to understood, and it makes the design more intuitive. |
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| Keywords: | asynchronous sequential logic clock signal next state Karnaugh map sequential waveforms |
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