简单高性能微处理器的设计

提高指令级并行度是处理器体系结构发展的重要方向,也是当前计算机组织、计算机结构课程的重要内容之一。为使学生对指令流水线、超标量等技术有更深入的理解和体会,本文介绍了一个简单的具有超标量流水线结构的微处理器模型的设计思想。针对在指令并行执行过程中出现的数据相关冲突,提出了指令相关性检查算法和数据相关性检查算法。论述了如何利用VHDL语言的特点,准确描述硬件的并行性及系统模块的划分,给出了模拟及仿真验证的例子。

A Design of a Simple High Performance Microprocessor

Improving the degree of the instruction level parallelism is not only an important trend for the development of the CPU architecture but also significant content of the course about "Computer Organization", "Computer Architecture". This paper introduces a design of a simple microprocessor model with superscalar pipelined technology, providing the students an opportuninty to comprehend instruction level parallelism, superscalar pipelined technology and so on. The instruction dependency checking algorithm and the data dependency checking algorithm are brought up in this paper to settle the conflict of the correlative data happening in the executing of instruction. In addition, this paper disusses how to use VHDL to describe the parallelism of hardware and the partition of the system module. For validation, an example of simulation and emulation is also offered in this paper.