| FPGA控制下面阵CCD时序发生器设计及硬件实现 |
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| 引用本文： | 朱冰莲,杜培强,运明华.FPGA控制下面阵CCD时序发生器设计及硬件实现[J].电子科技,2011,24(6):127-130,133. |
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| 作者姓名： | 朱冰莲 杜培强 运明华 |
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| 作者单位： | (重庆大学 通信工程学院,重庆 400044) |
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| 摘 要： | 在分析Sony公司ICX098BQ面阵CCD图像传感器驱动时序的基础上,对可调节曝光时间的CCD时序发生器及其硬件电路进行设计.选用FPGA器件作为硬件设计平台,使用VHDL语言对时序关系进行了硬件描述,采用QuARTUSⅡ8.0对所设计的时序发生器进行了功能仿真,并以Altera公司的可编程逻辑器件为核心进行硬件适配...
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| 关 键 词： | 面阵CCD FPGA 时序发生器 |
Design of a Driving Schedule Generator for the Area Array CCD Controlled by FPGA |
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| ZHU Binglian,DU Peiqiang,YUN Minghua.Design of a Driving Schedule Generator for the Area Array CCD Controlled by FPGA[J].Electronic Science and Technology,2011,24(6):127-130,133. |
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| Authors: | ZHU Binglian DU Peiqiang YUN Minghua |
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| Affiliation: | (College of Communication Engineering,Chongqing University,Chongqing 400044,China) |
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| Abstract: | In this paper,driving timing of Sony ICX098BQ area array CCD image sensor is analyzed.CCD timing generator with adjustable exposure time and its hardware circuit are designed.FPGA is chosen as the hardware design platform,and schedule generator is described with VHDL.The designed generator successfully fulfills function simulation with Quartus II 8.0 and fit into FPGA made by Altera.Actual tests show that driving schedule generator meets the driving requirement of area array CCD and achieves the design obje... |
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| Keywords: | FPGA |
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