| 一种低相位噪声采样时钟源的设计 |
| |
| 引用本文： | 蒋小强,石玉,苏安刚,赵宝林.一种低相位噪声采样时钟源的设计[J].电子科技,2014,27(6):39-41,45. |
| |
| 作者姓名： | 蒋小强 石玉 苏安刚 赵宝林 |
| |
| 作者单位： | (电子科技大学 微电子与固体电子学院,四川 成都 610054) |
| |
| 摘 要： | 分析了锁相环频率合成器与数字直接频率合成器的原理,阐述了二者性能的优劣。并在此基础上设计了一款低相位噪声的采样时钟源。该频率源结合锁相环和直接数字频率合成器的优势,在75 MHz时相位噪声可达-119 dBc@1 kHz、-116 dBc@100 kHz。
|
| 关 键 词： | 频率源 数字直接频率合成器 滤波器 相位噪声 |
Design of a Sampling Clock with Low Phase Noise |
| |
| JIANG Xiaoqiang,SHI Yu,SU Angang,ZHAO Baolin.Design of a Sampling Clock with Low Phase Noise[J].Electronic Science and Technology,2014,27(6):39-41,45. |
| |
| Authors: | JIANG Xiaoqiang SHI Yu SU Angang ZHAO Baolin |
| |
| Affiliation: | (School of Microelectronics and Solid Electronics,University of Electronic Science and Technology of China,Chengdu 610054,China) |
| |
| Abstract: | This paper introduces the theories of phase locked loop and direct digital synthesis, discusses their advantages and disadvantages, and presents the design of a sampling clock with low phase noise using the PLL and DDS technologies. The measurement results show that the phase noise is up to - 119 dBc@ 1 kHz and - 116 dBc@ 100 kHz at 70 MHz. |
| |
| Keywords: | phase locked loop digital direct synthesis filter phase noise |
| 本文献已被 CNKI 维普 等数据库收录！ |
| 点击此处可从《电子科技》浏览原始摘要信息 |
|
点击此处可从《电子科技》下载全文 |
|
