| 用VHDL语言实现数字钟设计 |
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| 引用本文： | 李彦强,赵淑明.用VHDL语言实现数字钟设计[J].山西电子技术,2014(5):38-39. |
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| 作者姓名： | 李彦强 赵淑明 |
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| 作者单位： | 天津三星光电子有限公司,天津301700 |
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| 摘 要： | 介绍了利用VHDL硬件描述语言进行数字钟的设计,具有调节时、分、秒和整点报时功能,并通过数码管驱动电路,动态显示计时结果。采用VHDL语言设计数字电路系统是当今的趋势,是我国在世界市场上生存竞争和发展的需要。
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| 关 键 词： | VHDL语言 数字钟 设计 |
The Design of Clock Based on VHDL |
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| Li Yanqiang,Zhao Shuming.The Design of Clock Based on VHDL[J].Shanxi Electronic Technology,2014(5):38-39. |
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| Authors: | Li Yanqiang Zhao Shuming |
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| Affiliation: | ( Tianjin Samsung Opto-electronics Co. ,Ltd, Tianjin 301700, China) |
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| Abstract: | The paper introduces the design of clock based on VHDL, which can correct the hour, minute, second and can ＇alarm at the right time. The time of clock can be displayed with the digital driving circuits. Designing the digital system with VHDL language is the trend of development of our electronic industry in the global market. |
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| Keywords: | VHDL language digital clock design |
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