基于重定时的高性能控制电路间接测试生成方法

对性能驱动控制逻辑进行测试生成难度较大,通常要加入可测性结构,但会影响原电路优化性能并增加生产成本.本文以重定时理论为基础,提出了对高性能时序电路进行间接测试生成的方法,这种方法在不影响原电路任何优化特性的前提下,可显著降低测试生成时间,提高测试生成质量.在ISCAS’89部分基准电路进行实验,结果证明了其有效性.

An Retiming-based Indirect Test Generation for Performance-Driven Control Logic

Since high performance control logics are usually hard for non-scan test generation,DFT structures could be embedded as offsets in tradition,while it will cause manufacturing cost increase and performance overhead.In this paper,an indirect test generation method based on retiming is proposed,which could dramatically reduce the cost of non-scan ATPG without any loss of original optimized attributes.Experiments on some ISCAS'89 benchmarks show the benefits of our approach in enhancing ATPG of performance-driven logic.