动态随机存储器中堆叠电容器结构的互连寄生电容模拟

在高密度比特位动态随机存储器(DRAM)芯片的发展中,随着多层布线与复杂存储单元结构的日渐普遍使用,互连寄生电容对存储器件性能如时延、功耗、噪声等的影响日渐突出,已成为不可忽视的重要因素,对互连寄生电容提取软件提出了紧迫的要求.本文介绍一个基于直接边界元素法的精度高,速度快,并可适应复杂堆叠(stacked)电容器结构的互连寄生电容模拟软件,并通过实例计算,分析DRAM中互连线寄生电容对电路性能的影响.

Simulation of the Parasitic Interconnect Capacitance in the DRAM with the Stacked Structures

With development of high density bit DRAM,the parasitic interconnect capacitance is becoming an important factor to affect the circuit performance such as time delay,power consumption and noise etc.While the multi level interconnection and complex storage capacitor cell are used in DRAM layout to increase the integrated density and improve performance of the integrated circuits,a powerful parasitic interconnect capacitance simulator is required urgently.A simulator based on the BEM,with high precision,high speed and strong ability to treat complicated structures,is presented in this paper.Some tested results of the parasitic interconnect capacitance are used to analyse the performance in DRAM circuits.