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基于FPGA和DSP实现的实时图像压缩
引用本文:赵保军,史彩成,毕莉,安建波,毛二可.基于FPGA和DSP实现的实时图像压缩[J].电子学报,2003,31(9):1317-1319.
作者姓名:赵保军  史彩成  毕莉  安建波  毛二可
作者单位:北京理工大学电子工程系,北京 100081
基金项目:国家 8 63计划项目 (No .2 0 0 2AA81 30 32 )
摘    要:利用FPGA的并行分布流水特点,选用exilinx公司的50万门级芯片XCV400E,设计并实现CIF格式(352×288象素)图像实时DCT变换.该设计采用乒乓模式,只需设计一个快速算法模块(F×CT)就解决了C×F×CT的实现算法.当视频信号通过数字化后逐行输入FPGA,在行、场同步信号和采样时钟的控制下,每输入一组数据(8个),就进行行向量与CT的矩阵乘运算(F×CT),并将结果按转置方式保存,每输入一个数进行一次(1×8)×(1×8)矩阵运算,每行进行352×(1×8)×(8×8)次矩阵运算,其中44次(1×8)×(8×8)矩阵运算的结果需要按转置形式(HT=(F×CT)T)存储;当输入下一组8行数据时,对该组数据进行与前述8行数据相同的矩阵运算,而对刚做完(F×CT)运算的8行相应结果,则按正常顺序取出进行(HT×CT)运算,将结果按转置形式(GT=C×H)输出.从而以实时流水的方式完成C×F×CT运算.功能仿真、时序仿真和与TMS320C62X系统的成功对接验证了本设计及算法的正确性.

关 键 词:DCT  乒乓模式  并行流水  
文章编号:0372-2112(2003)09-1317-03
收稿时间:2002-05-23

Implementation of Real-Time 2D-DCT with FPGA and DSP
ZHAO Bao jun,SHI Cai cheng,BI li,AN Jian bo,MAO Er ke.Implementation of Real-Time 2D-DCT with FPGA and DSP[J].Acta Electronica Sinica,2003,31(9):1317-1319.
Authors:ZHAO Bao jun  SHI Cai cheng  BI li  AN Jian bo  MAO Er ke
Affiliation:Dept.of Electronic Engineering,Beijing Institute of Technology,Beijing 100081,China
Abstract:Because of the FPGA's parallel pipelining processing features,this paper designed and implemented the real time CIF format image DCT using Exilinx Company's 500000 gate grade chip XCV400E.Using ping-pong model,C×F×CT is implemented only by designing one fast algorithm model (F×CT).Digital video signal is input to FPGA line by line.Controlling by horizontal sync and vertical sync,every group data of 8 pixels as a vector is input and is multiplied CT i.e.(F×CT).The computed results are stored as transform format.Each pixel needs one (1×8)×(8×8) matrix operations.Each line needs 352×(1×8)×(8×8) times matrix operations.44times (1×8)×(8×8) matrix operations results need storing as transform format (HT=(F×CT)T).When next 8 line data are input,they are processed with the same way as the above.For the last 8 line's first processed results (F×CT),they are read out and processed as (HT×CT).The final results are output as transform format (GT=C×H).Therefore,the continuous real-time whole field pix DCT transform C×F×CT is finished.Function and timing simulation and the successful connection with TMS320C62X system verified the design and implement.
Keywords:DCT  ping pong model  parallel pipelining process
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