基于弹性网稀疏表示的芯片参数成品率估算方法

当前集成电路芯片参数成品率估算通常预设大量扰动基函数进行芯片性能模型构建，易造成成品率估算方法复杂度过高.而若随意减少扰动基函数数量，则极易造成成品率估算精度缺失.针对此问题，本文提出一种芯片参数成品率稀疏估算方法.该方法首先根据工艺参数扰动建立具有随机不确定性的漏电功耗模型；然后按照关键度高低，利用弹性网自适应选取关键扰动基函数对漏电功耗模型进行稀疏表示建模；最后，利用贝叶斯理论及马尔科夫链方法对漏电功耗成品率进行估算.实验结果表明，该方法不仅可以使所构建的漏电功耗模型具有一般性和稀疏性优点，而且能够对漏电功耗成品率进行准确估算，与蒙特卡罗仿真结果相比估算误差不超过5%.同时，相较于蒙特卡罗采样，该方法还可以大幅减少算法仿真时间，具有更好的仿真效率.

An Efficient Estimation Method for Chip-Level Parametric Yield Based on Elastic Net Sparse Representation

Previous approaches on integrated circuit parametric yield estimation usually model chip performance by pre-setting variation basis functions.It is easy to result in high complexity.On the other hand,random reduction of the number of the basis functions may result in accuracy loss.In order to avoid the issues,a sparse estimation approach for chip-level parametric yield is proposed.Taking power yield as an instance,the proposed approach models leakage power stochastically.Then according to the importance level,several key basis functions are adaptively selected to constribute a sparse leakage power model based on elastic net.Finally according to Bias theory and Markov chain method,the power yield is estimated efficiently.Experimental results show that the proposed approach not only makes the established power model general and sparse,but estimates the power yield accurately.Comparing to Monte Carlo (MC) simulation,the relative errors of power yield estimation based on proposed method are less than 5％.In addition,this approach can lead to a large cost reduction compared with MC simulation,and thus has higher efficiency.