采用环型运放的12-bit 40-MS/s采样保持电路设计实现

为了保证模数转换器转换速度和精度，本文基于0.18微米工艺，设计实现了一款应用于12-bit 40-MS/s流水线ADC前端的采样保持电路.所采用的环型结构运放，可以简化设计、且占用面积小；同时，采用绝缘体上硅工艺，可以消除栅压自举开关中开关管的衬偏效应，改善开关的线性度，提高采样保持电路的性能.采样保持电路面积是0.023平方毫米.测试结果表明：在1.5V供电电压下，采样保持电路功耗是3.5mW；在1MHz输入频率、40MHz采样频率下，该采样保持电路无杂散动态范围可以达到76.85dB，满足12-bit 40-MS/s流水线模数转换器应用需求.

Implementation of a 12-bit 40-MS/s Sample-and-Hold Circuit with a Ring Amplifier

In order to keep the analog to digital converter' s speed and precision,a sample-and-hold (S/H) circuit for a 12-bit 40-MS/s pipeline ADC is designed and fabricated using a 0.18 micrometer process.The proposed amplifier can simplify the design and occupies smaller area.The substrate bias effect of the switch transistor used in the bootstrapped switch can be eliminated with the silicon-on-insulator (SOI) process,which can increase the linearity of bootstrapped switch and improve the performance of the S/H circuit.The S/H circuit occupies an area of 0.023 square millimeter.Measurement results show that the S/H circuit operates at a 1.5 V supply and consumes 3.5mW,and the spurious free dynamic range is 76.85 dB for a 1 MHz input signal with 40 MS/s sampling rate.The S/H circuit meets the requirement of the 12-bit 40-MS/s pipeline analog to digital converter.