| VLSI集成电路参数成品率及优化研究进展 |
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| 引用本文： | 郝跃,荆明娥,马佩军.VLSI集成电路参数成品率及优化研究进展[J].电子学报,2003,31(Z1):1971-1974. |
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| 作者姓名： | 郝跃 荆明娥 马佩军 |
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| 作者单位： | 西安电子科技大学微电子研究所, 陕西, 西安, 710071 |
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| 基金项目： | 国家高技术研究发展计划(863计划)，2003AA1Z1630， |
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| 摘 要： | VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素,随着集成电路(IC)进入超深亚微米发展阶段,芯片工作速度不断增加,集成度和复杂度提高,而工艺容差减小的速度跟不上这种变化,因此参数成品率的研究越来越重要.本文系统地讨论了参数成品率的模型和设计技术研究进展,分析不同技术的特点和局限性.最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向.
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| 关 键 词： | VLSI设计方法学 参数成品率 最优化设计 |
| 文章编号： | 0372-2112(2003)12A-1971-04 |
| 收稿时间： | 2003-11-17 |
| 修稿时间： | 2003年11月17 |
State of the Art on Study of Parametric Yield and Its Optimization for VLSI |
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| HAO Yue,Jing Ming-e,Ma Pei-jun.State of the Art on Study of Parametric Yield and Its Optimization for VLSI[J].Acta Electronica Sinica,2003,31(Z1):1971-1974. |
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| Authors: | HAO Yue Jing Ming-e Ma Pei-jun |
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| Affiliation: | Research Inst. of Microelectronics, Xidian University, Xi'an, Shaanxi 710071, China |
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| Abstract: | Parametric Yield of VLSI is an important factor related with manufactory cost and circuit performance.With development of deep sub-micron IC technologies,chips have led to a large increase in system complexity and the number of devices per die as well as the switching speeds.These advances have been accompanied by parametric yield loss due to the fluctuations in the manufactory process.Firstly,models and design technology of parametric yield is systematically discussed in this paper.Their advantages and disadvantages are discussed in details.Finally,the main problems and developing direction of parametric yield design and enhancement in very deep sub-micron regime are given. |
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| Keywords: | VLSI design methodology parametric yield optimal design |
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