Systolic arrays for Viterbi processing in communication systemswith a time-dispersive channel

The theory and design of systolic arrays for Viterbi processing in communication systems with a time-dispersive time-varying channel is discussed. The architecture, algorithms, and processor elements, for a two-dimensional systolic array are described. The array supports the branch metric computations required for an adaptive Viterbi processor. The array is designed so that computations propagate along the rows of the array, while data symbols propagate along the columns. All interprocessor data flow and connections within the array are nearest-neighbor. The array illustrates how the Viterbi-processor algorithms can be structured to achieve a high degree of computational concurrency. Variations in the array design are described and evaluated in terms of computational resource requirements and utilization and computational throughput. A high-bandwidth memory interface is proposed, and system design considerations are discussed