From defects creation to circuit reliability - A bottom-up approach (invited) |
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Authors: | V Huard F Cacho A Bravaix |
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Affiliation: | a STMicroelectronics, Crolles2 alliance, 850 rue Jean Monnet, 38926 Crolles, France b IM2NP-ISEN, UMR CNRS 6137, Maison des Technologies, place G. Pompidou, 83000 Toulon, France |
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Abstract: | This paper presents a theoretical framework about interface states creation rate from Si-H bonds at the Si/SiO2 interface. It includes three mains ways of bond breaking. In the first case, the bond can be broken thanks to the bond ground state rising with an electrical field. In the two others cases, incident carriers will play the main role either if there are very energetic or very numerous but less energetic. This concept allows us physically modeling the reliability of MOSFET transistors, and particularly NBTI permanent part, and Channel Hot Carrier (CHC) to Cold Carrier (CCC) damage. Finally, the translation of these physical models into reliability spice models is discussed. These models pave the way to Design-in Reliability (DiR) approach which seeks to provide a quantitative assessment of reliability - CMOS device reliability in this case - at design stage thereby enabling judicious margins to be taken beforehand. |
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Keywords: | Channel cold carriers Hot-Carrier degradation Ultra-thin gate-oxide Interface traps generation Border traps Trapped oxide charges Device lifetime Multi vibrational excitation Bias temperature stress Design-in Reliability Spice models |
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