功能可配置的数字变频芯片的研制与测试

为满足数字相控阵雷达对收发通道关键元器件国产化的需求,基于国内工艺线研制了一款数字变频芯片。该芯片包含双通道的数字下变频(DDC)与数字上变频(DUC)电路,通过LVDS 接口与SPI接口实现与上位机的数据交换。该芯片的抽取率/ 插值率、数字本振频率、相位偏置、通道幅度补偿系数、滤波器系数等参数均可配置,能够适应不同工作场景。通过修改数字变频器中数控振荡器(NCO)的相位偏置,可以实现对收发信号的移相操作,使与本芯片配对使用的TR组件可以取消移相器。通过门控时钟等低功耗设计大大降低了该芯片的平均功耗,减轻了供电与散热压力。经过芯片测试,该芯片的DDC与DUC的通带纹波<0. 05 dB,阻带衰减>70 dBc,平均功耗<1. 2 W,其功能与性能满足系统应用,为相控阵雷达收发通道的小型化与国产化提供了新的解决方案。

Development and Test of Digital Frequency Conversion Chip with Configurable Function

In order to meet the requirement of the localization of the key components of the digital phased array radar,a digital frequency conversion chip has been developed based on the domestic technology line. The chip is composed of dual channel digital down conversion (DDC) and digital up conversion ( DUC) circuit, could exchange data with FPGA through the LVDS interface and SPI interface. In order to adapting different working situations, the working parameter of the chip, such as the extraction rate,the interpolation rate, the digital local oscillator frequency, the phase offset, the channel amplitude compensation coefficient and the filter coefficients can be modified. By modifying the phase offset of the numerically controlled oscillator( NCO) in the digital converter, the phase shift operation of the receiver and transmitter can be realized, so the TR components that are paired with the chip can cancel the phase shifter. The average power consumption of the chip is greatly reduced by the low power consumption design of the clock gating, and the power supply and the heat radiation pressure are reduced. After the chip test, the chip DDC and DUC pass band ripple <0. 05 dB, stop band attenuation >70 dBc, average power consumption <1. 2 W. The function and performance of the chip meet the application requirements of the system. It provides a new solution for the miniaturization and localization of the phased array radar.