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Designing in reliability in advanced CMOS technologies
Authors:CR Parthasarathy  M Denais  V Huard  G Ribes  D Roy  C Guerin  F Perrier  E Vincent  A Bravaix
Affiliation:aSTMicroelectronics, Crolles 2 Alliance, 850, Rue Jean Monnet, Crolles 38926, France;bPhilips Semiconductors, Crolles 2 Alliance, 850, Rue Jean Monnet, Crolles 38926, France;cL2MP – ISEN, UMR CNRS 6137, Maison des Technologies, place G.Pompidou, 83000 Toulon, France
Abstract:Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper presents selected topics relevant to realize an efficient design-in reliability methodology in the latest generation CMOS technologies. NBTI is discussed in terms of characterization using On-The-Fly (OTF) methodology. Extension of OTF method is discussed using bias patterns to gain insights into NBTI under analog operation. A reliability simulation methodology is discussed against requirements for optimization and integration within an existing design flow. The features of this methodology are illustrated using some simple design examples.
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