Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits |
| |
| Affiliation: | 1. Groupe de Recherche en Microélectronique et Microsystèmes, Polytechnique de Montréal, Montréal, QC, Canada;2. Department of ECE, Tennessee Technological University, Cookeville, TN, United States;3. Department of ECE, Concordia University, Montréal, QC, Canada;1. School of Chemistry and Environment, South China Normal University, Guangzhou 510006, PR China;2. National Testing Center for Optical Radiation Safety of Photoelectric Products, Huizhou 516003, PR China;3. EVE Energy Co. Ltd, Huizhou 516006, PR China;1. Department of Statistics, Alpen-Adria-Universität Klagenfurt, Klagenfurt, Austria;2. Infineon Technologies Austria AG, Villach, Austria;1. Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Cerdanyola del Valles, Spain;2. Departamento de Materia Condensada, GIA, GAIANN, CAC, Comisión Nacional de Energía Atómica, Buenos Aires, Argentina;1. Department of Electrical Engineering, Tampere University of Technology, P.O. Box 692, 33101 Tampere, Finland;2. Konecranes Plc, P.O. Box 661, 05830 Hyvinkää, Finland;1. School of Reliability and Systems Engineering, Beihang University, Beijing 100191, China;2. Avic Aviation Motor Control System Institute, Wuxi 214000, China;3. Center for Advanced Life Cycle Engineering (CALCE), University of Maryland, USA |
| |
| Abstract: | Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits. |
| |
| Keywords: | Soft errors MDG Higher abstraction level SER SEGP-Finder Asynchronous |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
