Solder void position and size effects on electro thermal behaviour of MOSFET transistors in forward bias conditions |
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| Affiliation: | 1. VeDeCoM Institute, 77 rue des Chantiers, F-78000 Versailles, France;2. IFSTTAR-LTN, 25 allée des Marronniers, F-78000 Versailles, France;1. Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Cerdanyola del Valles, Spain;2. Departamento de Electricidad y Electrónica, Universidad de Valladolid, Valladolid, Spain;3. Department of Chemistry, University of Helsinki, Helsinki, Finland;1. SAGE-ENISo, National Engineering School of Sousse, 4023 University of Sousse, Tunisia;2. Al Leith Engineering College, Umm Al-Qura University, Saudi Arabia;3. ISIM, University of Gabes, 6072 Gabes, Tunisia;4. ESTACA Research Center, 92532 Levallois Perret, Paris, France;5. GPM-UMR CNRS 6634, University of Rouen, 76801 Saint Etienne du Rouvray, France;1. Le2i, UMR CNRS 6306, University of Burgundy, 9 Avenue Alain Savary, 21000 Dijon, France;2. Centre National d’Etudes Spatiales (CNES), 18 Avenue Edouard Belin, 31401 Toulouse, France;1. STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles Cedex, France;2. Laboratory of Computer Sciences, Paris 6 (LIP6), Systems On Chips Department, UPMC University, 4 place Jussieu, 75252 Paris Cedex 05, France;1. University of Vienna, Physics of Nanostructured Materials, Vienna, Austria;2. Materials Center Leoben Forschung GmbH, Leoben, Austria;3. Vienna University of Technology, Faculty of Technical Chemistry, Vienna, Austria;1. Engineering Product Development Pillar, Singapore University of Technology and Design, Singapore 138 682, Singapore;2. Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA 02139, USA |
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| Abstract: | This research aims to enhance the understanding on position and size effects on the electro thermal behaviour of low voltage power MOSFET transistors in forward bias condition. The numerical simulations are based on a fractional design of experiments (DoE). The performance of a finite elements model is discussed by comparing thermal and electrical measurements to results of finite elements simulation on a module of free void and voided solder. The void in the model is afterwards parameterized on position and size, according to the fractional DoE of the study. The combined functions issued from the parametric simulations and the DoE show the main impact of void size on temperature of the device and on the surface temperature of the bonding wires. From the numerical viewpoint, the most impacting position of void depends highly on the void size. The redistribution of current density and temperature on MOSFET chip and bonding wires due to solder void is also observed. A future experimental study in respect to the same DoE is expected in prospect, in order to fulfil the complementarity for this approach. |
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| Keywords: | MOSFET Solder void effect Forward bias conditions Fractional design of experiments |
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