Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection

This study aims at developing an advanced clamped through-silicon via (C-TSV) interconnection technology for three-dimensional (3D) chip-to-chip or chip-to-wafer packaging. The special features of the C-TSV technology include (1) the proposal of metal caps on the pads of the chip to form a nearly symmetric double-side-metal-cap structure that firmly clamps the vias on the chip, (2) the employment of a temporary conductive layer on the active side of the wafer as a seed metal layer during the electro-plating of metal caps, and (3) the introduction of a “via first redistribution” (VFR) concept in the C-TSV process for heterogeneous 3D integration and maximal performance. Basically, the metal caps can act as a bonding layer for 3D chip stacking and also a protection stopper for backside drilling. The blind vias are created using a proven low-cost laser drilling process through the wafer backside with a laminated insulation layer on the via-hole wall. Unlike the typical TSV process, the present technology has no need to carry out the seed layer deposition and photo processes to facilitate the via-hole filling with metal through electro-plating, thus being more cost-effective. Besides, because of the structural symmetry and also the tightly-clamped via structure, it can potentially yield better bonding reliability for stacked chip bonding. To demonstrate the effectiveness of the C-TSV structure for wafer-level 3D integration, feasibility study of the implementation of the novel process and mechanics comparisons of these two 3D chip stacking structures under thermal loading through finite element (FE) stress simulation are made. At last, both the thermal humidity (TH) test of 85 °C/85%RH and the 288 °C solder dipping test are carried out to demonstrate the interconnect reliability and the interface quality of the 3D interconnect technology.