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CCD时序与基于时分复用的实时数据处理系统设计
引用本文:李华.CCD时序与基于时分复用的实时数据处理系统设计[J].电视技术,2012,36(19).
作者姓名:李华
作者单位:商洛学院,陕西商洛,726000
基金项目:商洛学院科研基金资助项目
摘    要:分析并设计了e2v公司的CCD42-80 Back Illuminated AIMO型CCD器件驱动时序,完成了一种既节省硬件资源,又能实时、准确输出图像数据的CCD数据处理系统.采用了曝光时间可调节设计来适应相机观测目标的多变性,使用时分复用技术结合乒乓操作、后进先出(LiFo)等技术,保证了图像的质量和实时性.应用一片可编程门阵列FPGA作为硬件设计载体,使用Verilog-HDL硬件描述语言并采用自上而下的模块化设计对整个系统进行硬件描述.在系统时钟64 MHz、图像输出速率200 kHz条件下,测试结果表明,时序电路工作正常,可以满足CCD相机的驱动要求,相机系统输出的图像实时、稳定.基本满足了观测系统对CCD相机在成像和数据传输方面的要求.

关 键 词:CCD  驱动时序  时分复用  LiFo  乒乓操作
收稿时间:3/4/2012 12:00:00 AM
修稿时间:2012/4/17 0:00:00

Design of CCD Timing Generator and Real-Time Data Processing system Based on Time-Division Multiplexing
lihua.Design of CCD Timing Generator and Real-Time Data Processing system Based on Time-Division Multiplexing[J].Tv Engineering,2012,36(19).
Authors:lihua
Affiliation:Shangluo University
Abstract:Driving schedules of CCD 42-80 Back Illuminated AIMO manufactured by e2v have been examined and designed. One CCD-data processing system which improves the utility of hardware resource, obtains real-time image have been designed. Exposure time adjustment is adopted to adapt the changeful observation environment. Based on time-division multiplexing technology combined with ping-pong operation and LIFO, high quality real-time image is obtained. One field programmable gate array (FPGA) is chosen as the hardware design platform, and the whole circuit is described with Verilog-HDL to perform the modularization design from top to bottom. When system clock is 64MHz and image read clock is 200KHz, experiments show that the driving circuit works normally and meets the design requirement, furthermore, the system can export real-time and vivid images. It can satisfy the observation system requirements of CCD camera in imaging and data transmission.
Keywords:CCD  Driving schedule  Time-division multiplexing  LIFO  Ping-pong operation
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