一种适用于多速率FIR滤波器的算法改进

多速率FIR滤波器是数字下变频的核心技术之一。由于高阶FIR数字滤波器使用了大量的乘法单元，在FPGA中将占用大量的逻辑资源(LE),这极大的限制了FPGA的设计。根据多倍抽取FIR滤波器的特性，提出了一种分时复用乘法单元以减少逻辑资源使用量的改进算法，大量节约了FPGA的逻辑资源。通过FPGA设计实现，在Quartus II中综合仿真结果中可以验证，设计基本达到预期效果，在满足设计要求的前提下，实现了节约逻辑资源的目的。

A improved method for multirate FIR filter

Multirate FIR filter is one of the core technology of digital down converter.Since the high order FIR filter use a large number of multiplication unit,it consume many logic resources of FPGA and extremely limit the design of FPGA. According to the feature of decimation filter, a improved method about time division multiplexing of multiplication unit is put forward. This method save a large number of logic unit. Through the FPGA and Quartus II software, this method is realized. According to the result of synthesize and simulation, the design achieve the desired effect. Under the premise of design requirements, it realize the aim of saving logic resources.