| 一种CMOS静态双沿顺序脉冲发生器的设计 |
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| 引用本文： | 葛丽颖,黄世震,林伟.一种CMOS静态双沿顺序脉冲发生器的设计[J].现代电子技术,2006,29(8):22-23,29. |
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| 作者姓名： | 葛丽颖 黄世震 林伟 |
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| 作者单位： | 福州大学,福建省微电子集成电路重点实验室,福建,福州,350002 |
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| 摘 要： | 提出一种基于CMOS技术的静态双沿顺序脉冲发生器结构。他是由以基于CMOS二选一选择器的电平型触发器构成的记忆单元和一个与门阵列组成的转译单元构成的。与门阵列的转译单元使顺序脉冲发生器在时钟上升沿和下降沿处均能输出移位脉冲,从而形成双沿触发的功能。仿真验证其功能正确,且根据分析该结构不仅能够节省芯片面积,还可以大大减小芯片的功耗。
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| 关 键 词： | CMOS 双沿顺序脉冲发生器 功耗 与门阵列 |
| 文章编号： | 1004-373X（2006）08-022-02 |
| 收稿时间： | 2005-10-14 |
| 修稿时间： | 2005-10-14 |
A CMOS Static Double-Edge-Triggered Sequential-Pulse-Generator |
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| GE Liying,HUANG Shizhen,LIN Wei.A CMOS Static Double-Edge-Triggered Sequential-Pulse-Generator[J].Modern Electronic Technique,2006,29(8):22-23,29. |
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| Authors: | GE Liying HUANG Shizhen LIN Wei |
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| Affiliation: | Mieroelectronic Integrated Circuit Lab of Fujian. Fuzhou University, Fuzhou, 3500052, China |
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| Abstract: | This paper presents a CMOS static doubleedgetriggered sequentialpulsegenerator.The novel design involves a memorizing unit on the basis of CMOS leveltriggers and a unit of an AND gates array.This array of AND gates can make the sequentialpulsegenerator output sequentialpulse at both rising and falling edge.The simulation results have demonstrated that this SPG has ideal logic functionality,lower power dissipation and less area. |
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| Keywords: | CMOS double-edge-triggered sequential-pulse-generator power dissipation gate array |
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