FPGA设计中的跨时钟域问题

随着FPGA设计中的时钟频率越来越高,时钟方案越来越复杂,跨时钟域问题变成了设计和验证中的关键点。为了解决跨时钟域问题对FPGA设计造成功能错误,对跨时钟域信号采用两级寄存器或多级寄存器同步、握手协议和异步FIFO等同步方法;同时还提出了不检查时序、修改SDF文件和添加约束文件三种仿真中的技术,解决了跨时钟域产生的亚稳态现象对FPGA仿真验证造成的影响。

Problem of clock domain crossing in FPGA design

With the increasing clock frequency in the FPGA design,the clock scheme is more and more complex,and the issue of crossing the clock domain becomes a key point in design and verification. In order to correct the function error in FPGA design generated by crossing clock domain,two-stage register or multi-stage register synchronization,hand-shake protocol and asynchronous FIFO are used for the signal crossing the clock domain. At the same time,some technologies of no-timing check, SDF file modification and constraint file addition are proposed,which overcome influence of metastable state phenomennon pro-duced by clock domain crossing on FPGA simulation and verification.