| Gbps试验系统中高速串行接口的设计与实现 |
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| 引用本文： | 王向阳,赵艳杰.Gbps试验系统中高速串行接口的设计与实现[J].现代电子技术,2008,31(22). |
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| 作者姓名： | 王向阳 赵艳杰 |
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| 作者单位： | 东南大学,移动通信国家重点实验室,江苏,南京,210096 |
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| 基金项目： | 国家高技术研究发展计划(863计划) |
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| 摘 要： | 介绍Gbps无线通信试验系统中高速串行数据接口的设计与实现。按照Gbps无线通信试验系统对高速串行数据的传输要求,数据传输速率超过1 Gb/s,在基于Xilinx IP core技术上对单板上的FPGA进行逻辑设计,实现了符合系统要求的高速串行数据接口。在系统实际调试中,通过ATCA机箱背板进行数据传输,获得了高达Gbps的数据吞吐速率且传输误码率低于10-14。
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| 关 键 词： | Gbps 高速串行接口 FPGA ATCA |
Design and Implementation of High Speed Serial I/O Interface in Gbps Experimental System |
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| WANG Xiangyang,ZHAO Yanjie.Design and Implementation of High Speed Serial I/O Interface in Gbps Experimental System[J].Modern Electronic Technique,2008,31(22). |
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| Authors: | WANG Xiangyang ZHAO Yanjie |
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| Abstract: | The design and implementation of high speed serial I/O interface in the Gbps wireless communication experimental system is presented in this paper.In accordance with requirements of high speed serial data transmission in the Gbps wireless communication experimental system,the data transmission rate surpasses 1 Gb/s.The high speed serial data interface module is implemented by carrying on logic design in FPGAs of single boards based on Xilinx IP core.According to actual system debugging,the data throughput up to Gbps is achieved by data transmission through ATCA chassis with full-mesh backplane.The bit error rate is below 10-14. |
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| Keywords: | Gbps high speed serial interface FPGA ATCA |
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