一种高性能低复杂度的LDPC译码器的FPGA实现

低密度校验码(LDPC码)所具有的优越性能和实用价值使其已经成为编码领域研究的热点。然而实际中LD-PC码的应用还有许多具有挑战性的问题,像如何降低译码的复杂度以及如何减少译码所需的大量硬件资源等。基于以上原因,研究一种高性能、低复杂度的软判决译码算法。这种译码算法较常用的硬判决译码算法性能出色,同时较一般的迭代译码算法的收敛速度快,并且可以部分并行译码,需要的存储量很小,能够大幅度降低LDPC译码的硬件实现复杂度,具有实际应用价值。

FPGA Implement for High Performance and Low Complex LDPC Decoder

For high performance and great value,most of scientists on channel-coding have great interested in Low Density Parity-Check Code(LDPC).But there are many problems unsolved,such as how to reduce the implement complexity,how to cut down the hardware resource and so on.For these reasons,a study on soft-decision decoding arithmetic has been carried out.The arithmetic has high performance,high convergence and so on.The side-by-side decoding can be used to implement the decoder,which makes design has low memory-stored and low hardware implantation complexity.So the design has great value for practice utility.