Turbo码高速译码器设计

Turbo码具有优良的纠错性能,被认为是最接近香农限的纠错码之一,并被多个通信行业标准所采用。Turbo码译码算法相比于编码算法要复杂得多,同时其采用迭代译码方式,以上2个原因使得Turbo码译码器硬件实现复杂,而且译码速度非常有限。从Turbo码高速译码器硬件实现出发,介绍Turbo码迭代译码的硬件快速实现算法以及流水线译码方式,并介绍利用Altera的Flex10k10E芯片实现该高速译码器硬件架构。测试和仿真结果表明,该高速译码器具有较高的译码速度和良好的译码性能。

Design of the High Speed Turbo Decoder

Turbo code is considared as one of error-correcting codes which has performance to the Shannon Bound,and is adopted by many communication standards.Turbo decoding algorithm is much more complex compared to coding algorithm,with an iterative decoding method.For these reasons,Turbo decoder is implemented complexly only with low speed usually.In this paper,the speed implementation algorithm and the pipeline decoding concept are introduced,and a hardware architecture of a speed decoder used with Flex10k10E is presented.The tested and simulated results show the high speed and the good performance of the decoder.