| 10～37GHzCMoS四分频器的设计 |
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| 引用本文： | 沈炎俊,冯军.10～37GHzCMoS四分频器的设计[J].国外电子元器件,2009(11):79-80. |
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| 作者姓名： | 沈炎俊 冯军 |
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| 作者单位： | 东南大学射频与光电集成电路研究所; |
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| 基金项目： | 国家863计划项目(2006AA01Z284) |
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| 摘 要： | 给出基于0．13μmCMOS工艺、采用单时钟动态负载锁存器设计的四分频器。该四分频器由两级二分频器级联而成。级间采用缓冲电路实现隔离和电平匹配。后仿真结果表明其最高工作频率达37GHz，分频范围为27GHz。当电源电压为1．2V、工作频率为37GHz时，其功耗小于30mW，芯片面积为0．33-0．28mm2。
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| 关 键 词： | 光纤通信系统 CMOS工艺 动态负载锁存器 分频器 |
Design of 10-37GHz CMOS divide-by-4 frequency divider |
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| SHEN Yan-jun,FENG Jun.Design of 10-37GHz CMOS divide-by-4 frequency divider[J].International Electronic Elements,2009(11):79-80. |
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| Authors: | SHEN Yan-jun FENG Jun |
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| Affiliation: | SHEN Yan-jun,FENG Jun(Institute of RF & OE-ICs,Southeast University,Nanjing 210096,China) |
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| Abstract: | A divide-by-4 frequency divider based on single clock dynamic-loading latches in 0.13μm complementary-metal- oxide-semiconductor（CMOS） technology is presented. It consists of two levels of divide-by-2 frequency divider. A buffer circuit is inserted between them to realize separation and the level matching.The post-simulation shows that it exhibits the maximum operating frequency which is up to 37GHz,and achieves a frequency range of 27GHz.While operating at 37GHz with the 1.2V supply voltage ,the power dissipation is less than 30roW,The chip area is 0.33×0.28mm2. |
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| Keywords: | optic-fiber communication system CMOS technology dynamic-loading latch frequency divider |
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