| 基于FPGA的全数字锁相环的设计 |
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| 引用本文： | 王文理,张霞.基于FPGA的全数字锁相环的设计[J].国外电子元器件,2009,17(1):39-40,43. |
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| 作者姓名： | 王文理 张霞 |
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| 作者单位： | 河北大学电子信息工程学院; |
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| 摘 要： | 简单介绍了全数字锁相环(ADPLL)的结构和工作原理,提出一种在FPGA的基础上可增大全数字锁相环同步范围的设计方法,并给出了部分verilog HDL设计程序的代码和仿真波形。
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| 关 键 词： | FPGA ADPLL（全数字锁相环） verilog HDL SOC（片上系统） |
Design of all digital phase locked loop based on FPGA |
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| WANG Wen-li,ZHANG Xia.Design of all digital phase locked loop based on FPGA[J].International Electronic Elements,2009,17(1):39-40,43. |
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| Authors: | WANG Wen-li ZHANG Xia |
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| Affiliation: | College of Electronic and Information Engineering;Hebei University;Baoding 071002;China |
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| Abstract: | The system structure and the principle of ADPLL is introduced.A design way of all digital phase locked loop that will increase synchronous range based on PFGA is proposed in detail,and the partial verilog HDL code and simulation wave-form is given. |
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