Générateur de machines séquentielles autotestables pour circuits intégrés spécifiques

This paper presents an original method using a ROM memory, of systematically synthesizing on-line and offline self-testing synchronous sequential machines (automata, sequencers,), for the design of compiled ASIC’S. Choices about state transition graph coding and circuit architecture are related to simplicity, compactness, operating rate and especially to testability. The on-line and off-line testing is based on an error detecting code of a recurrent type: in addition to useful data, the ROM memory contains redundant information which is distributed between two consecutive states. This method guarantees both present state coherence and past transition conformity. On-line testing is based in this type of coding, called distributed redundancy coding. Its fault coverage is given for different classes of hardware failures. Off-line testing, which is exhaustive, uses the distributed redundancy coding technique and consists in scanning all the possible graph transitions in memory address order.