基于FPGA的全加器硬宏设计及优化

现场可编程门阵列（FPGA）是目前应用非常广泛的一种专用集成电路。在FPGA平台上实现了2位全加器硬宏的设计,同时深入FPGA平台底层对该全加器硬宏所占用的切片资源和响应时间进行了优化,并且从逻辑上证明了该设计的正确性。在此基础上,可以非常方便地使用该硬核搭建任意2n位的全加器。最后通过该设计的应用与仿真,再次验证了其高效性和正确性,从而实现了最初的目的,即大幅度地提高基于FPGA的全加器设计的密度和速度。

Hardcore Design and Optimization Based on FPGA for Full-adder

FPGA is a most useful ASIC in many fields.A full 2-bit adder is designed with the hardcore on the FPGA platform.And deep into the bottom of the FPGA platform,the resource of slice and the speed of response for this hardcore full-adder are optimized.This design is proved correct and efficient in logic.So any 2 n-bit full-adder based on this hardcore could be built up.Finally,the application and simulation indicates that this hardcore design is correct and highly efficient.Thus the initial purpose in great enhancement of the density and the speed of this design is completely realized.