| 一种全数字时钟数据恢复电路的设计与实现 |
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| 引用本文： | 江黎,钟洪声.一种全数字时钟数据恢复电路的设计与实现[J].通信技术,2008,41(11). |
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| 作者姓名： | 江黎 钟洪声 |
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| 作者单位： | 电子科技大学电子通信大楼704教研室,四川成都,610054 |
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| 摘 要： | 时钟数据恢复(CDR)电路是数据传输系统的重要组成部分.对于突发的数据传输,传统的锁相环法很难达到其快速同步的要求.对此,文中提出一种改进型超前滞后锁相环法的全数字时钟恢复算法,与同类电路比较,具有数据码率捕获范围宽、辅获时间短的优点.文中还介绍了用FPGA来完成该电路设计.理论分析、仿真和实际测试表明,对非归零码,该电路的码率捕获范围5-20 MHz,20 MHz码率时相位抖动容限为2 ns.
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| 关 键 词： | 时钟数据恢复 数据传输 数字锁相 同步 |
Design and Implementation of An All Digital Clock and Data Recovery Circuit |
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| JIANG Li,ZHONG Hong-sheng.Design and Implementation of An All Digital Clock and Data Recovery Circuit[J].Communications Technology,2008,41(11). |
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| Authors: | JIANG Li ZHONG Hong-sheng |
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| Affiliation: | JIANG Li,ZHONG Hong-sheng (College of Electronics Engineering,University of Electronic Science , Techelonigy of Chengdu,Chengdu Sichuan 610054,China) |
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| Abstract: | Clock Date Recovery (CDR) circuit is a important part of data transmission equipment. For the burst data transmission, the traditional phase-lock loop can hardly achieve the requirement of fast synchronization. Whereof, this essay is trying to put forward an improved Lead and Lag Control all-numeric CDR calculation, which is characterized with wide frequency capture range and rapid capture time. This essay also puts forward the circuit design based on FPGA. By theoretical analysis, simulation and practical ... |
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| Keywords: | clock data recovery data transmission digital phase-lock synchronization FPGA |
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