闪存控制器中BCH编解码器设计和验证

工艺的进步和消费电子市场对高密度非易失性存储的需求,促使多层单元闪存代替单层单元闪存成为闪存市场的主流,但同时提出数据可靠性的需求。针对多层单元闪存中存在的多比特随机错误问题,闪存控制器中需要实现低功耗高带宽的BCH编解码器。设计采用8 bit的并行编解码,每1 024 Byte能纠正32 bit的随机错误。关键方程步骤采用简化伯利坎普-梅西算法,优化逻辑。功能仿真和FPGA原型验证证明设计的正确性。

Design and Verification of BCH ENCODER/DECODER for Flash Controller

The demand for high-density non-volatile storage by technological advance and consumer electronics market,promotes the replacement of Single-Layer Cell(SLC) by Multi-Level Cell(MLC) as the mainstream of flash memory market,but at the same time raises the demand for data reliability.To overcome random error bits in MLC,it is necessary for flash controller to implement a low-power high-throughput BCH encoder/decoder.In this paper,8 bit parallel encode/ decode is introduced,which could correct 32 bit random error per 1 024 byte.The key equation is solved by Simplified inverse-free Berlekamp-Massey algorithm(SiBM),thus to optimize the logics.Functional simulation and FPGA prototype verification indicate the correctness of this design.