| 嵌入式UART的设计及FPGA验证 |
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| 引用本文： | 朱勤,钱敏,杨翠军,朱静.嵌入式UART的设计及FPGA验证[J].通信技术,2012,45(1):150-153. |
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| 作者姓名： | 朱勤 钱敏 杨翠军 朱静 |
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| 作者单位： | 1. 苏州大学电子信息学院微电子系,江苏苏州215006;苏州工业职业技术学院,江苏苏州215104
2. 苏州大学电子信息学院微电子系,江苏苏州,215006 |
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| 摘 要： | 随着微电子技术的发展,IP核成为SOC IC设计技术的关键;UART(通用异步收发器)作为输入/输出系统中重要的基本组成部分,设计其IP核并嵌入SOC系统中具有十分重要的应用意义。采用自上而下的设计方法,设计系统各模块并集成、仿真,最后在Xilinx ISE 9.1i开发环境下进行了综合、仿真和FPGA器件下载进行硬件实现、验证。结果表明设计正确,功能稳定、可靠。UART IP核能很好的应用到SOC中去,具有很高的使用价值。
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| 关 键 词： | RS232 片上系统 UART IP核 状态机 现场可编程门阵列 |
Design and FPGA Verification of Embedded UART |
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| ZHU Qin
,
QIAN Min
,
YANG Cui-jun
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ZHU Jing.Design and FPGA Verification of Embedded UART[J].Communications Technology,2012,45(1):150-153. |
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| Authors: | ZHU Qin QIAN Min YANG Cui-jun ZHU Jing |
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| Affiliation: | 1.School of Electroncs ＆ Information, Soochow University, Suzhou Jiangsu 215006, China; 2.Suzhou Institute of Industrial Technology, Suzhou Jiangsu 215104, China) |
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| Abstract: | With the development of micro-electronic technology, IP core becomes the key technology for SOC design. Universal Asynchronous Receiver Transmitter IP core （UART）, working as a widely-used input / output system, is an important component in SOC system. The top-down technology is adopted to design various modules of the system and implement integration and simulation, and the design is verified in FPGA. The experiment result indicates that the design is correct, and the function is stable and reliable. |
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| Keywords: | RS232 SOC UART IP core FSM FPGA |
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