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Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement |
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| Authors: | Jena Sisir Kumar Biswas Santosh Deka Jatindra Kumar |
| Affiliation: | 1.Department of CSE, IIT, Guwahati, India ;2.Department of EECS, IIT, Bhilai, India ; |
| Abstract: | Journal of Electronic Testing - Applications like Recognition, Mining, and Synthesis (RMS) with error-resilience properties can use circuits that produce acceptable results. In other words, the... |
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