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基于BiCMOS工艺的版图与原理图匹配验证
引用本文:蔡斌君,黄其煜,龚大卫.基于BiCMOS工艺的版图与原理图匹配验证[J].半导体技术,2007,32(7):593-597.
作者姓名:蔡斌君  黄其煜  龚大卫
作者单位:上海交通大学,微电子学院,上海,200030;上海先进半导体制造股份有限公司,上海,200233;上海交通大学,微电子学院,上海,200030;上海先进半导体制造股份有限公司,上海,200233
摘    要:从BiCMOS工艺着手,结合一个基本的基准电路,从实施命令文件编写的角度,重点论述了模拟集成电路的版图与原理图匹配验证中的一个重要环节,即器件的正确识别与图层间节点信息的传输.就其中易出现的一些问题,逐一提出了具体的解决方案,同时借助专业验证平台演示了如何运用图层间的逻辑运算,将其中一些处理技巧转化为可以被验证程序执行的语言,以达到快速、准确验证的目的.验证的实际结果证明这些解决方案是可行并有效的.

关 键 词:匹配验证  命令文件  节点  逻辑运算  器件识别
文章编号:1003-353X(2007)07-0593-05
修稿时间:2007-01-30

LVS Verification Based on BiCMOS Process
CAI Bin-jun,HUANG Qi-yu,GONG Da-wei.LVS Verification Based on BiCMOS Process[J].Semiconductor Technology,2007,32(7):593-597.
Authors:CAI Bin-jun  HUANG Qi-yu  GONG Da-wei
Affiliation:1. School of Microelectronics, Shanghai JiaoTong University, Shanghai 200030, China ; 2. Advanced Semiconductor Manufacturing Corporation Limited, Shanghai 200233, China
Abstract:With a basic reference circuit as an example,key point of layout versus schematic(LVS) verification based on a BiCMOS process was discussed,which was device recognition and nodal information transfer between layers.Then the detailed solutions to some key issues in compiling the command file of LVS were provided,which were proved to be feasible and effective by the running results with the aid of professional verification platform.Relating skills of logic operation between the drawing layers to handle those problems were also illustrated.
Keywords:LVS  command file  node  logic operation  device recognition
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