| 一种高效时钟树综合实现方法 |
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| 引用本文： | 邓尧之,万培元,刘世勋,林平分.一种高效时钟树综合实现方法[J].半导体技术,2012,37(3):169-171,179. |
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| 作者姓名： | 邓尧之 万培元 刘世勋 林平分 |
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| 作者单位： | 北京工业大学北京市嵌入式系统重点实验室,北京,100124;北京工业大学北京市嵌入式系统重点实验室,北京,100124;北京工业大学北京市嵌入式系统重点实验室,北京,100124;北京工业大学北京市嵌入式系统重点实验室,北京,100124 |
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| 基金项目： | 北京工业大学博士科研启动基金 |
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| 摘 要： | 针对ASIC芯片设计中时钟树综合效率和时序收敛的问题,提出了一种高效的时钟树综合方法,特别适用于现代先进深亚微米工艺中的高集成度、高复杂度的设计中。改进了传统时钟树综合方法,通过采用由下至上逐级分步综合的方法实现。该设计方法在SMIC 0.18μm eflash工艺下的一款电力线载波通信芯片中成功流片验证,结果表明分步综合能够在实现传统设计功能的前提下,在完成时序收敛时有效减少不必要的器件插入,从而减小芯片面积,降低整体功耗,有效改善绕线拥塞度。
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| 关 键 词： | 时序收敛 时钟树综合(CTS) 片上系统 时钟偏差 缓冲器 |
Method of Efficient Clock Tree Synthesis |
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| DengYaozhi
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Wan Peiyuan
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Liu Shixun
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Lin ping fen.Method of Efficient Clock Tree Synthesis[J].Semiconductor Technology,2012,37(3):169-171,179. |
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| Authors: | DengYaozhi Wan Peiyuan Liu Shixun Lin ping fen |
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| Affiliation: | (Beijing Embedded System Key Lab,Beijing University of Technology,Beijing 100124,China) |
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| Abstract: | A new method was proposed to solve the problem of clock tree synthesis(CTS)efficiency and timing closure.This method was suitable for modern highly sophisticated and integrated deep sub-micron VLSI design.The traditional CTS was optimized and it was realized by a bottom-up step-by-step synthesis approach.A power-line-communication chip design was used to verify the proposed method in a 0.18 μm eflash CMOS technology.The result shows that based on this method,the functionality was successfully realized,excess buffers were avoided during timing closure.As a result,the chip area and power consumption can be reduced and the congestion improved. |
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| Keywords: | time closure clock tree synthesis(CTS) system on chip(SoC) clock skew buffer |
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