50V LDMOS漏电容非线性研究

借助软件模拟从器件结构和工艺参数角度研究了LDMOS漏电容Cd的非线性和源漏电压Vds的关系,研究了漂移区注入剂量、高压场板长度、场氧化层厚度、栅氧化层厚度、沟道区注入剂量等五个结构工艺参数对漏电容非线性的影响.主要分析了漂移区耗尽层对漏电容非线性的影响机理以及不同结构工艺参数如何通过改变漂移区耗尽层电容,进而影响漏电容非线性.提出了改善LDMOS的漏电容线性度的各参数调节方法.

Nonlinear Analysis on Drain Capacitance of 50 V LDMOS

The relationship between nonlinear drain-capacitance Cd of LDMOS and the drain-source voltage Vds was researched at the aspect of device structure and process parameter by simulation.The influences of five parameters(the doses of the drift,the length of the field plate,the thickness of field oxide layer,the thickness of gate oxide layer,the doses of the channel) on the nonlinear Cd were discussed.The influence of drift depletion layer on the nonlinear Cd,and the influence of the five parameters on the drift depletion layer were analysed.The methods to improve the linearity of Cd were proposed.