一种带电流源校准的16bit高性能DAC

设计了一种带电流源校准电路的16 bit高速、高分辨率分段电流舵型数模转换器(DAC)。针对电流舵DAC中传统差分开关的缺点,提出了一种优化的四相开关结构。系统分析了输出电流、积分非线性和无杂散动态范围(SFDR)三个重要性能指标对电流舵DAC的电流源单元设计的影响,完成了电流源单元结构和MOS管尺寸的设计。增加了一种优化设计的电流源校准电路以提高DAC的动态性能。基于0.18μm CMOS工艺完成了该DAC的版图设计和工艺加工,其核心部分芯片面积为2.8 mm^2。测试结果表明,在500 MHz采样速率、100 MHz输入信号频率下,测得该DAC的SFDR和三阶互调失真分别约为76和78 dB,动态性能得到明显提升。

A 16 bit High Performance DAC with Current Source Calibration

A 16 bit high speed and resolution segmented current-steering digital-to-analog converter(DAC)with a current source calibration circuit was designed. Aiming at the defect of traditional diffe-rential switch in current-steering DACs, an optimized quad-switch structure was proposed. Influences of three important performance indexes of output current, integral nonlinearity and spurious free dynamic range(SFDR) on the current source unit design of the current-steering DAC were systematically analyzed, and the designs of the current source unit structure and MOS transistor size were completed. An optimized current source calibration circuit was added to improve the dynamic performance of the DAC. Based on the 0.18 μm CMOS process, the layout design and processing of the DAC were completed, and the core chip area is 2.8 mm^2. The test result shows that at 500 MHz sample rate and 100 MHz input signal frequency the SFDR and third-order inter-modulation distortion of the DAC are about 76 and 78 dB, respectively. The dynamic performance of the DAC is significantly improved.