| 高速专用GFP处理器的FPGA实现 |
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| 引用本文： | 牛燚坤,徐智勇,乔庐峰,陈德军.高速专用GFP处理器的FPGA实现[J].光通信技术,2009,33(11). |
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| 作者姓名： | 牛燚坤 徐智勇 乔庐峰 陈德军 |
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| 作者单位： | 1. 解放军理工大学,通信工程学院,南京,210007
2. 中国人民解放军94860部队,南京,210047 |
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| 摘 要： | 采用FPGA实现了非标准用户数据接入SDH网络时,进行数据GFP封装和解封装的处理器电路.在处理器电路中引入了缓冲区管理器,使得电路能够有效处理突发到达、瞬时速率较高的客户数据;采用了并行CRC算法,进一步地提高了GFP处理器的处理速度.GFP处理器在xilinx xc2vp2上实现,共占用大约700个4输入查找表,采用80MHz系统工作时钟,8位数据总线宽度时,数据处理能力可达640Mb/s.
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| 关 键 词： | 并行CRC |
Implementation in FPGA of the high speed and customization GFP processor |
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| NIU Yi-kun,XU Zhi-yong,QIAO Lu-feng,CHEN De-jun.Implementation in FPGA of the high speed and customization GFP processor[J].Optical Communication Technology,2009,33(11). |
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| Authors: | NIU Yi-kun XU Zhi-yong QIAO Lu-feng CHEN De-jun |
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| Affiliation: | NIU Yi-kun1,XU Zhi-yong1,QIAO Lu-feng1,CHEN De-jun2(1.Institute of Communications Engineering,PLA University of Science and Technology,Nanjing 210007,China 2.Unit 94860 of PLA,Nanjing 210047,China) |
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| Abstract: | The paper use FPGA realized the GFP processor circuit which used to pack and unpack the nonstandard user data that will be transferred by SDH.The application of buffer manage made circuit can deal with the data of abrupt arrived and instantaneous high speed effectively.To adopt the parallel CRC arithmetic further improved the compute speed of GFP processor.The GFP processor realized in xilinx xc2vp2, which needs approximately 700 4-input LUTs,and adopts 80MHz system clock,the width of data bus is 8,the capa... |
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| Keywords: | SDH GFP FPGA SDH GFP FPGA parallel CRC |
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