基于DDS 与PLL 的C 波段宽带线性扫频源

利用直接数字频率合成(DDS)和锁相环(PLL)技术相结合的混合频率合成方案,研制了一种C波段宽带、高频率分辨率、快速线性扫频的频率源。为了给PLL 提供低相位噪声的宽带扫频参考信号,选用ADI 的DDS芯片AD9914,并利用阶跃恢复二极管(SRD)高次倍频电路结合二倍频器产生高达3400 MHz 的时钟信号。通过上位机配置AD9914 内部频率调谐字和数字斜坡发生器,产生512.5-987.5MHz 的扫频参考信号,其频率分辨率可精细到赫兹量级。选用低附加噪声的鉴相器和宽带VCO 芯片设计C 波段锁相源,在宽带工作频率范围内对DDS 扫频信号进行快速跟踪,并有效抑制杂散信号。实测结果表明,该扫频源工作频率为4. 1- 7. 9 GHz,在频率分辨率配置为0. 38 MHz 时,单向扫频周期为1 ms,扫频线性度为1. 58×10-6 。单频点输出时相位噪声优于-114 dBc/ Hz@ 10 kHz和-119 dBc/ Hz@ 100 kHz,杂散抑制优于69 dBc。

C Band Wideband Linear Frequency-Swept Source Based on DDS and PLL

A wideband frequency-swept source at C band with high frequency resolution and high linear sweep speed is developed based on a hybrid scheme of direct digital frequency synthesis (DDS) and phase locked loop (PLL) techniques. In order to provide the PLL with a low-phase-noise wideband frequency-swept reference signal, ADI''s DDS IC AD9914 is chosen in this design. A step recovery diode (SRD)-based high-order multiplier chain combined with a frequency doubler is employed to generate the DDS''s clock signal with frequency up to 3400MHz. By configuring the frequency tuning word and digital ramp generator inside the AD9914, a sweeping reference signal with a frequency range of 512.5-987.5MHz is gener- ated, with a frequency resolution as fine as Hertz scale. The C band PLL is designed based on a low noise phase-frequency detector and a wideband VCO. The PLL tracks the DDS''s sweeping signal at a high speed and suppresses the spurious signals effectively in a specified wide frequency range. The measured results show that the operating frequency covers 4.1-7.9GHz, the one-way sweep period is 1ms and sweep linearity is 1.58×10-6 when the frequency resolution is configured as 0.38 MHz. The measured phase noise is lower than -114dBc/ Hz@ 10kHz and -119dBc/ Hz@100kHz, and the spurious suppression is better than 69dBc for single frequency signals delivered by the frequency source.