A lifetime-aware analog circuit sizing tool

Reliability of CMOS circuits has become a major concern due to substantially worsening process variations and aging phenomena in deep sub-micron devices. As a result, conventional analog circuit sizing tools have become incapable of promising a certain yield whether it is immediately after production or after a certain period of time. Thereby, analog circuit sizing tools have been replaced by better ones, where reliability is included in the conventional optimization problem. Variation-aware analog circuit synthesis has been studied for many years, and numerous methodologies have been proposed in the literature. On the other hand, to our best knowledge, there has not been any tool that takes lifetime into account during the optimization. Besides, there are a number of different issues with lifetime-aware circuit optimization. For example, aging analysis is still quite problematic due to modeling and simulation deficiencies. Furthermore, a challenging trade-off between efficiency and accuracy is revealed during lifetime estimation in the optimization loop. Relatively expensive aging analysis is carried out for each candidate solution corresponding to a large number of simulations, so it is extremely important to deal with this trade-off. With regard to aforementioned these problems, this study proposes a novel lifetime-aware analog circuit sizing tool, which utilizes a novel deterministic aging simulator with adjustable step size. Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) mechanisms are considered during the lifetime analysis, where the NBTI model was developed via accelerated aging experiments through silicon data. As case studies, two different OTA circuits are synthesized and results are provided to discuss the proposed tool.