Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems

In this paper, a four-stage method for synthesizing reconfigurable ASNoC topology is proposed for partially dynamically reconfigurable systems, where the topology is reconfigured dynamically at run-time along with the application's execution. Firstly, a simulated annealing based topology-aware integrated optimization framework is proposed to generate the proper schedule and floorplan of task modules. Secondly, based on the schedule and floorplan of task modules, an Integer Linear Programming (ILP)-based method and a heuristic method, are proposed to partition the communication requirements of the application into $T$ time intervals. Thirdly, we explore the proper positions of switches in the floorplan for global communications. Finally, considering the reconfiguration costs between adjacent time intervals, the routing path allocation problem is solved for time intervals in an iterative procedure to generate fine-grained dynamically reconfigurable ASNoC topologies. Experimental results show that, compared to the random partition of communication requirements, the proposed heuristic method and ILP-based method can achieve 5.4% and 10.0% power consumption improvement, respectively. And, the reconfigurable ASNoC can achieve 31.6% power consumption improvement when compared with static ASNoC.