FPGA-based implementation of classification techniques: A survey |
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| Affiliation: | 1. Institute of Physical Education and Health, Huaihua University, Huanhua, HuNan, 418000, China;2. HeBei Institute of Communications, Shijiazhuang, HeBei, 050071, China;1. Electrical and Electronic Engineering Department, Auckland University of Technology, Auckland 1010, New Zealand;2. Department of IT and Software Engineering, Auckland University of Technology, Auckland 1010, New Zealand;1. Department of Computer Engineering, University of Texas at Dallas, Richardson, 75080, USA;2. Department of Electrical Engineering, University of Texas at Dallas, Richardson, 75080, USA |
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| Abstract: | Recently, a number of classification techniques have been introduced. However, processing large dataset in a reasonable time has become a major challenge. This made classification task more complex and expensive in calculation. Thus, the need for solutions to overcome these constraints such as field programmable gate arrays (FPGAs). In this paper, we give an overview of the various classification techniques. Then, we present the existing FPGA based implementation of these classification methods. After that, we investigate the confronted challenges and the optimizations strategies. Finally, we highlight the hardware accelerator architectures and tools for hardware design suggested to improve the FPGA implementation of classification methods. |
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| Keywords: | Machine learning Deep learning Classification Implementation Optimizations Challenges |
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