Efficient design of magnitude and 2's complement comparators |
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| Affiliation: | 1. Department of Electrical and Computer Engineering, National Technical University of Athens, 10682, Athens, Greece;2. Department of Informatics and Computer Engineering, University of West Attica, 12210, Egaleo, Athens, Greece;1. The School of Electronics and Information Engineering, Lanzhou Jiaotong University, Lanzhou 730070, China;2. Lanzhou Jiaotong University, Lanzhou 730070, China;1. CNRS & LSV, ENS Paris-Saclay, 61, avenue du Président Wilson, Cachan Cedex 94235, France;2. LRI, Université Paris-Sud, Bât 650, Rue Noetzlin, Gif-sur-Yvette 91190, France;3. Department of Computer Science, Yonsei University, 50, Yonsei-Ro, Seodaemun-Gu, Seoul 03722, Republic of Korea;4. Department of Mathematics and Statistics, University of South Florida 12010 USF Cherry Drive, Tampa, FL 33620, USA |
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| Abstract: | Digital comparators are important arithmetic components used in digital systems to determine if two numbers are equal, or if one number is greater or less than the other. In this work, the design of magnitude and 2's complement comparators is examined. New OR-based full tree and simplified tree magnitude comparator architectures are proposed. The existing and the proposed comparator architectures are implemented in standard cell technology and evaluated, after extensive experimental analysis, in high performance and relaxed conditions. The proposed comparators operate faster than the existing ones, while operating at the same speed yield significant improvement in area complexity and power dissipation. |
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| Keywords: | Digital arithmetic Magnitude comparators 2's complement comparators |
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