A new realization scheme for dynamic PFSCL style |
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| Affiliation: | 1. Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, 110042, India;2. Department of Electronics and Communication Engineering, Bharati Vidyapeeth''s College of Engineering, Delhi, 110063, India;1. Department of Engineering, University of Perugia, Terni, Italy;2. DIEM, University of Salerno, Fisciano (SA), Italy;3. DIMES, University of Calabria, Rende (CS), Italy;1. Department of Electrical and Electronics Engineering, Trakya University, Edirne 22180, Turkey;2. Department of Electrical and Electronics Engineering, Istanbul Sehir University, Istanbul 34662, Turkey |
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| Abstract: | In this paper, a new scheme of logic function realization in dynamic positive feedback source-coupled logic (D-PFSCL) style is proposed. The existing scheme implements only NOR/OR based realization of a logic function. Thus, a complex function in D-PFSCL has high gate count which degrades the overall circuit performance measured in terms of power and delay. This paper therefore aims to resolve the issue by proposing a scheme which modifies the structure of a D-PFSCL gate. The modified gate exhibits AND/OR functionality and is used to realize various functions. Simulations have been carried out by implementing various functions and comparing their performance with the existing schemes at 1 GHz. The results of performance comparison with existing schemes indicates significant reuduction in gate count resulting in overall performance improvement. |
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| Keywords: | low Power Mixed-signals circuits Source-coupled logic PFSCL Dynamic PFSCL |
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